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ET1810, ET1811 | EtherCAT IP core for Altera FPGAs

The EtherCAT IP core enables the EtherCAT communication function and application-specific functions to be implemented on an FPGA (Field Programmable Gate Array – i.e. a device containing programmable logical components). The EtherCAT functionality is freely configurable. The IP core can be combined with own FPGA designs and offers the option of communicating with a soft core processor via the Avalon® interface. The physical interfaces and internal functions, such as the number of FMMUs and SYNC managers, the size of the DPRAM, etc., are adjustable. The process data interface (PDI) and the distributed clocks are also configurable. The functions are compatible with the EtherCAT specification and the EtherCAT ASICs (ET1100, ET1200).

The ET1811 (Altera®) quantity-based licence offers manufacturers of small lots and development service providers the possibility of entering the world of EtherCAT development with low initial investment. For the development of an EtherCAT device, the ET1811 one-time kick-off charge is required, plus ET1811-1000 royalty for 1,000 devices. The royalties for 1,000 devices must be paid in advance each time.

Development service providers only require ET1811 one-time kick-off charge; the ET1811-0030 system integrator OEM licence is required for each customer implementation. The end customer requires the royalty licence (ET1811-1000).

The number of required logic elements depends on the chosen configuration:

EtherCAT IP core for Altera®:

  • 2 MII ports, 32 bit digital I/O, 1 kB RAM, without distributed clocks, with FMMU and SYNC manager, has approx. 6,900 logic elements
  • 3 MII ports, SPI interface, 60 kB RAM, 64 bit distributed clocks, 8 FMMUs and 8 SYNC managers, has approx. 25,500 logic elements

The EtherCAT Altera® IP core can be used with the following FPGAs: Cyclone®, Cyclone® II, Cyclone® III, Cyclone® IV, Stratix®, Stratix® II Stratix® III, Stratix® IV, Stratix® GX, Stratix® II GX, Arria® GX and Arria® II GX.

Configurable features ET1810, ET1811, ET1812
PHY interface 1…3 ports MII or 1…2 ports RMII
FMMUs 0…8
SYNC manager 0…8
DPRAM 1…60 kbyte
Distributed clocks 2 x SYNC outputs, 2 x latch inputs (32/64 bit)
Process data interfaces 32 bit digital I/O, SPI, 8/16 bit asynchronous µC interface, Avalon® interface, 64 bit general purpose I/O
Ordering information Description
Node-locked buy out licence
ET1810 Node-locked licence for using the EtherCAT IP core on one workstation. The licence includes 1 year maintenance and updates.
ET1810-0010 extension of the node-locked Altera® licence (ET1810) by one additional workstation
ET1810-0020 one-year maintenance extension for node-locked licence (ET1810)
Node-locked quantity-based licence
ET1811 one-time kick-off charge for the node-locked quantity-based licence for using the freely configurable EtherCAT IP cores on one workstation; target hardware: selected Altera® devices
ET1811-1000 royalty for 1,000 devices, ET1811 required
ET1811-0020 one-year maintenance extension, ET1811 required
ET1811-0030 system integrator OEM licence
Floating buy out licence
ET1812 floating buy out licence for Altera® FPGAs
ET1812-0010 extension of the floating licence (ET1812) by one additional workstation
ET1812-0020 one-year maintenance extension for floating licence (ET1812)
  Яндекс.Метрика